The present disclosure relates to diagnostic circuit elements, and more specifically, to physically aware insertion of diagnostic circuit elements.
In prior generation microprocessors, circuit elements for the purposes of diagnosing chip failures (such as XOR's in scan chains) were inserted with no consideration of physical layout properties. The result was poor spatial resolution for failure analysis, which made root cause defect identification difficult and time consuming due to large inspection areas. For example, as seen in FIG. 1, a graph of area insertion mean segment length and area is shown, according to conventional methods. The area insertion mean is depicted as a function of XOR frequency. Generally speaking, the size of the circle depicted in FIG. 1 represents how compact the circuits are in the layout. The large circle 1102 in the plot represents actual insertion properties for a 22 nm microprocessor product. The small circle 11 identifies an average logical resolution (y-axis) of ˜20 circuits while the diameter of large circle 1102 is proportional to the average spatial resolution of chip circuit elements. The logical resolution is the average number of devices that a diagnostic element can identify. For example, as shown in the graph of FIG. 1, for every one element inserted, about twenty normal circuits are identified. While a logical resolution of 20 circuit elements may be acceptable, the spatial resolution can make circuit analysis labor intense, time consuming, and costly.
The placement of diagnostic elements into scan chains can affect a great number of things, including chip failure analysis, circuit power analysis and management, and extrapolation of relevant scan chain diagnosis information from a limited circuit sample. Current diagnostic methods may include blind placement or singular-ruled placement of diagnostic circuit elements, and may not provide a clear metric having a broad set of rules that may be applicable when determining where diagnostic circuit elements should be placed.